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Workshop
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xBGAS: Toward a RISC-V ISA Extension for Global, Scalable, Shared Memory
Event Type
Workshop
Registration Categories
W
Tags
Memory
NVRAM
Parallel Programming Languages, Libraries, and Models
TimeSunday, November 11th11:14am - 11:30am
LocationD170
DescriptionGiven the switch from monolithic architectures to integrated systems of commodity components, scalable high performance computing architectures often suffer from unwanted latencies when operations depart an individual device domain. Transferring control and/or data across loosely coupled commodity devices implies a certain degree of cooperating in the form of complex system software. The end result being a total system architecture the operates with low degrees of efficiency.

This work presents initial research into creating micro architecture extensions to the RISC-V instruction set that provide tightly coupled support for common high performance computing operations. This xBGAS micro architecture extension provides applications the ability to access globally shared memory blocks directly from rudimentary instructions. The end result is a highly efficient micro architecture for scalable shared memory programming environments.
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