Presenter

Rafael Tornero Gavilá (male) received his Bachelor of Science + Master of Science in Computer Engineering (5-years full time degree) and Master of Advanced Studies (MAS) in Computational Mathematics and Computer Science from the Universitat de València in 2005 and 2008, respectively. He joined to the Networking and Virtual Environments Group (GREV) research group, at the Universitat de València in 2007 and got strong background in NoC design. He is a member of the Hipeac network of excellence, from which he has received a HiPEAC collaboration grant. Since 2014, R. Tornero is a member of the GAP research group. He has collaborated with different institutions (Catania, Jonkoping, Carnegie Mellon University). His research interests focus on FPGA-based System Design, specifically in every aspect involving manycore architectures (on-chip interconnects, coherence protocols, memory hierarchy, processor cores, etc.) and Hardware Accelerators for High Performance Computing (HPC). He is an expert on using the Xilinx Vivado Design tools and the PRODESIGN multi-FPGA platforms and tools. He participates in the H2020 FETHPC MANGO project as hardware architect of the Heterogeneous Node being developed in a PRODESIGN multi-FPGA platform and co-leads the integration of different IP Cores in the MANGO platform.