Presentation
Kennedy Award Presentation - Memory Consistency Models: They Are Broken and Why We Should Care
Presenter
Event Type
Awards Presentation
TP
EX
TimeWednesday, November 14th9:15am - 10am
LocationExhibit Hall B
DescriptionThe memory consistency model for a shared address space specifies the value a load can return, affecting programmability and performance. For such a fundamental property, it, unfortunately, still routinely causes heads to spin. I will first briefly trace the evolution of memory models over three decades. The 1990s saw an explosion in memory models from hardware vendors and researchers. The 2000s drove a convergence centered on the more software-centric view of the data-race-free model. The last decade has struggled with mind-twisting implications of “out-of-thin-air” values and relaxed atomics, pointing to a fundamentally broken paradigm for hardware and software.
The end of Moore’s law is driving transformational change in hardware with specialization and heterogeneity within and across chips, including application-specialized and heterogeneous parallelism, coherence, and communication. How does this affect the memory model, or more broadly, the hardware-software interface? From our recent research in the DeNovo project, I will show examples of how we are again in danger of repeating the mistakes of the hardware-centric 1990s to create another memory model mess. On the other hand, there is a golden opportunity for hardware-software cooperation to redefine our interface from the ground up and find a fundamental resolution to the problem. I believe this will require rethinking how we represent parallelism, communication, and correctness in software, how we provide coherence and communication in hardware, and that the HPC community’s expertise in how to explicitly manage communication will have a key role to play.
The end of Moore’s law is driving transformational change in hardware with specialization and heterogeneity within and across chips, including application-specialized and heterogeneous parallelism, coherence, and communication. How does this affect the memory model, or more broadly, the hardware-software interface? From our recent research in the DeNovo project, I will show examples of how we are again in danger of repeating the mistakes of the hardware-centric 1990s to create another memory model mess. On the other hand, there is a golden opportunity for hardware-software cooperation to redefine our interface from the ground up and find a fundamental resolution to the problem. I believe this will require rethinking how we represent parallelism, communication, and correctness in software, how we provide coherence and communication in hardware, and that the HPC community’s expertise in how to explicitly manage communication will have a key role to play.
Presenter