Presentation
Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs
SessionTask-Based Programming
Event Type
Paper
TP
Algorithms
Architectures
Memory
Networks
Parallel Programming Languages, Libraries, and Models
Power
Programming Systems
Scheduling
TimeWednesday, November 14th11am - 11:30am
LocationC146
DescriptionWith increasing core counts, the scalability of directory-based cache coherence has become a challenging problem. To reduce the area and power needs of the directory, recent proposals reduce its size by classifying data as private or shared, and disable coherence for private data. However, existing classification methods suffer from inaccuracies and require complex hardware support with limited scalability.
This paper proposes a hardware/software co-designed approach: the runtime system identifies data that is guaranteed by the programming model semantics to not require coherence and notifies the microarchitecture. The microarchitecture deactivates coherence for this private data and powers off unused directory capacity. Our proposal reduces directory accesses to just 26% of the baseline system and supports a 64× smaller directory with only 2.8% performance degradation. By dynamically calibrating the directory size, our proposal saves 86% of dynamic energy consumption in the directory without harming performance.
This paper proposes a hardware/software co-designed approach: the runtime system identifies data that is guaranteed by the programming model semantics to not require coherence and notifies the microarchitecture. The microarchitecture deactivates coherence for this private data and powers off unused directory capacity. Our proposal reduces directory accesses to just 26% of the baseline system and supports a 64× smaller directory with only 2.8% performance degradation. By dynamically calibrating the directory size, our proposal saves 86% of dynamic energy consumption in the directory without harming performance.
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