<span class="var-sub_title">Power Aware Heterogeneous Node Assembly</span> SC18 Proceedings

The International Conference for High Performance Computing, Networking, Storage, and Analysis

Women in HPC: Diversifying the HPC Community

Power Aware Heterogeneous Node Assembly

Authors: Bilge Acun (IBM Research)

Abstract: To meet ever increasing computational requirements, supercomputers and data centers are beginning to utilize fat compute nodes with multiple hardware components such as manycore CPUs and accelerators. These components have intrinsic power variations even among same model components from same manufacturer. In this paper, we argue that node assembly techniques that consider these intrinsic power variations can achieve better power efficiency without any performance trade off on large scale supercomputing facilities and data centers. We propose three different node assembly techniques: (1) Sorted Assembly, (2) Balanced Power Assembly, and (3) Application-Aware Assembly. In Sorted Assembly, node components are categorized (or sorted) into groups according to their power efficiency, and components from the same group are assembled into a node. In Balanced Power Assembly, components are assembled to minimize node-to-node power variations. In Application-Aware Assembly, the most heavily used components by the application are selected based on the highest power efficiency. We evaluate the effectiveness and cost savings of the three techniques compared to the standard random assembly under different node counts and variability scenarios.

Archive Materials

Back to Women in HPC: Diversifying the HPC Community Archive Listing

Back to Full Workshop Archive Listing