<span class="var-sub_title">Challenges of High-Capacity DRAM Stacks and Potential Directions</span> SC18 Proceedings

The International Conference for High Performance Computing, Networking, Storage, and Analysis

MCHPC’18: Workshop on Memory Centric High Performance Computing

Challenges of High-Capacity DRAM Stacks and Potential Directions


Abstract: With rapid growth in data volumes and an increase in number of CPU/GPU cores per chip, the capacity and bandwidth of main memory can be scaled up to accommodate performance requirements of data-intensive applications. Recent 3D-stacked in-package memory devices such as high-bandwidth memory (HBM) and similar technologies can provide high amounts of memory bandwidth at low access energy. However, 3D-stacked in-package memory have limited memory capacity. In this paper, we study and present challenges of scaling the capacity of 3D-stacked memory devices by stacking more DRAM dies within a device and building taller memory stacks. We also present potential directions and mitigations to building tall HBM stacks of DRAM dies. Although taller stacks are a potentially interesting approach to increase HBM capacity, we show that more research is needed to enable high-capacity memory stacks while simultaneously scaling up their memory bandwidth. Specifically, alternative bonding and stacking technologies can be investigated as a potentially major enabler of tall HBM stacks.

Archive Materials

Back to MCHPC’18: Workshop on Memory Centric High Performance Computing Archive Listing

Back to Full Workshop Archive Listing