Hardware Transactional Persistent Memory

Student: Ellis Giles (Rice University)
Supervisor: Peter Varman (Rice University)

Abstract: This research solves the problem of creating durable transactions in byte-addressable Non-Volatile Memory or Persistent Memory (PM) when using Hardware Transactional Memory (HTM)-based concurrency control. It shows how HTM transactions can be ordered correctly and atomically into PM by the use of a novel software protocol. We exploit the ordering mechanism to design a novel persistence method that decouples HTM concurrency from back-end PM operations. Failure atomicity is achieved using redo logging coupled with aliasing to guard against mistimed cache evictions.

The algorithm uses efficient lock-free mechanisms with bounded static memory requirements and executes on existing Intel based processors. A back-end distributed memory controller alternative provides a hardware implementation choice for catching PM cache evictions. Our approach compares well with standard (volatile) HTM transactions and yields significant gains in latency and throughput over other persistence methods.

ACM-SRC Semi-Finalist: no

Poster: PDF
Poster Summary: pdf
Reproducibility Description Appendix: PDF


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