Moderator: Marc Snir (University of Illinois)
Panelists: Pavan Balaji (Argonne National Laboratory), Laxmikant Kale (University of Illinois), Vivek Sarkar (Georgia Institute of Technology), Sean Treichler (Nvidia Corporation), Hartmut Kaiser (Louisiana State University), Raymond Namyst (University of Bordeaux)
Abstract: We propose to discuss in the panel the following three assertions:
a) The coming decade is likely to see an accelerated evolution in programming models for HPC, for several reasons:
-- As Moore's law plateaus, increased performance requires increasingly heterogeneous platforms and asynchronous algorithms.
-- As platforms become more dynamic (e.g., due to dynamic power management) and algorithms become more adaptive, runtime adaptation is increasingly important. Asynchronous Task Models (ATM), such as Charm++, Legion, PaRSEC, etc., seem better suited to handle this evolution than the prevalent model of MPI+OpenMP.
b) The potential benefits of new programming models cannot fully realized without a more powerful runtime that better integrates internode and intranode synchronization and communication with local resource scheduling and memory management.
c) The development and deployment of new programming models, as well as more efficient support for current models can be accelerated by standardizing new interfaces that enable such integration
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