How to Analyze the Performance of Parallel Codes 101
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TimeSunday, November 11th8:30am - 5pm
DescriptionPerformance analysis is an essential step in the development of HPC codes. It will even gain in importance with the rising complexity of machines and applications that we are seeing today. Many tools exist to help with this analysis, but the user is too often left alone with interpreting the results.

We will provide a practical road map for the performance analysis of HPC codes and will provide users step-by-step advice on how to detect and optimize common performance problems, covering both on-node performance and communication optimization as well as issues on threaded and accelerator-based architectures. In addition, we will review current approached in ubiquitous monitoring of performance utilizing lightweight tools. Throughout this tutorial, we will show live demos using Open|SpeedShop, a comprehensive and easy to use tool set. Additionally, at the end of each section we will provide hands-on exercises for attendees to try out the new techniques learned with performance comparison across multiple architectures. All techniques will, however, apply broadly to any tool, and we will point out alternative tools where useful.
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