DescriptionBurst buffers have become increasingly popular in HPC systems, allowing bursty I/O traffic to be serviced faster without slowing down application execution. The ubiquity of burst buffers creates opportunities for studying their ideal placement in the HPC topology. Furthermore, the topology of the network interconnect can also affect the performance of the storage hierarchy for different burst buffer placement schemes. To that end, we create a reproducible framework that allows individual centers to develop their own models and evaluate performance based on their workload characteristics. We use CODES to create models that simulate the network and storage layers of an HPC system and Darshan traces for I/O replay. We augment the Darshan traces with synchronization primitives, and allow multi-dimensional scaling of traces to represent future workload characteristics. Finally, we evaluate the effect of network topology, storage architecture, and application I/O patterns on overall I/O performance.