Energy Efficiency of Reconfigurable Caches on FPGAs
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TimeThursday, November 15th8:30am - 5pm
DescriptionThe performance of a given cache architecture depends largely on the applications that run on it. Even though each application has its best-suited cache configuration, vendors of fixed HPC systems must provide compromise designs. Reconfigurable caches can adjust cache configuration dynamically to get best-suited cache parameters in runtime and notably reduce energy consumption. For example, when it is possible to deploy a low capacity low associativity design without increasing the miss rate substantially. For modern multi-core processors, each core's memory access behavior can be influenced by other cores. So it is more complicated to design reconfigurable caches for them.

In this paper, a design for a reconfigurable cache on FPGAs is presented that can run in modes with different capacities, associativity. We demonstrate that better performance and energy efficiency can be achieved by tuning these cache parameters at runtime.
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