The Data-Centric Future and Gen-Z's Next Generation Interconnect
TimeMonday, November 12th7pm - 9pm
DescriptionCurrent computer architectures allow for network and storage transfers to occur at much lower rates than memory transfers, so they must have separate buses, control signals, and command structures. Processors must wait endlessly for these transfers to finish or must find other work to do. A great deal of time is spent moving data between buffers to allow components working at highly different speeds to communicate effectively. Extra hardware is often needed to create DMA channels that perform transfers outside the normal flow of instructions and data. Resuming or cancelling partially completed transfers is difficult and error-prone. Gen-Z technology is different: a high-bandwidth, low-latency fabric with separate media and memory controllers that can be realized inside or beyond traditional chassis limits. Gen-Z enables much higher throughput and much lower complexity for big data solutions in such applications as data analytics, deep packet inspection, artificial intelligence, machine learning, and video and image processing.
The Gen-Z Consortium, an industry consortium comprised of over 50 leading technology companies, recently released its Core Specification 1.0 to the public.