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DTSTART:19700308T020000
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DTSTAMP:20181221T160742Z
LOCATION:D221
DTSTART;TZID=America/Chicago:20181113T161500
DTEND;TZID=America/Chicago:20181113T163000
UID:submissions.supercomputing.org_SC18_sess279_drs118@linklings.com
SUMMARY:Hardware Transactional Persistent Memory
DESCRIPTION:Doctoral Showcase\nArchitectures, Memory, Runtime Systems, Sto
 rage, Workshop Reg Pass, Tutorial Reg Pass, Tech Program Reg Pass, Exhibit
 s Reg Pass, Exhibits - Exhibit Hall Only Reg Pass, Doctoral Showcase\n\nHa
 rdware Transactional Persistent Memory\n\nGiles, Varman\n\nThis research s
 olves the problem of creating durable transactions in byte-addressable Non
 -Volatile Memory or Persistent Memory (PM) when using Hardware Transaction
 al Memory (HTM)-based concurrency control.  It shows how HTM transact
 ions can be ordered correctly and atomically into PM by the use of a novel
  software protocol.  We exploit the ordering mechanism to design a no
 vel persistence method that decouples HTM concurrency from back-end PM ope
 rations.  Failure atomicity is achieved using redo logging coupled wi
 th aliasing to guard against mistimed cache evictions.<br /><br />The algo
 rithm uses efficient lock-free mechanisms with bounded static memory requi
 rements and executes on existing Intel based processors.  A back-end 
 distributed memory controller alternative provides a hardware implementati
 on choice for catching PM cache evictions.  Our approach compares wel
 l with standard (volatile) HTM transactions and yields significant gains i
 n latency and throughput over other persistence methods.
URL:https://sc18.supercomputing.org/presentation/?id=drs118&sess=sess279
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