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DTSTART;TZID=America/Chicago:20181111T090000
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UID:submissions.supercomputing.org_SC18_sess170@linklings.com
SUMMARY:Fourth International Workshop on Heterogeneous High-Performance Re
 configurable Computing (H2RC'18)
DESCRIPTION:Workshop\nAccelerators, Heterogeneous Systems, NVRAM, Workshop
  Reg Pass\n\nIntroduction - Fourth International Workshop on Heterogeneous
  High-Performance Reconfigurable Computing (H2RC'18)\n\nBakos, Blott, Hoef
 ler, Cappello\n\nAs in the previous three years, this workshop will bring 
 together application experts, software developers, and hardware engineers,
  both from industry and academia, to share experiences and best practices 
 to leverage the practical application of reconfigurable logic to Scientifi
 c Computing, Machine/...\n\n---------------------\nPreserving Privacy thro
 ugh Processing Encrypted Data\n\nLeeser\n\nSecure Function Evaluation (SFE
 ) allows an interested party to evaluate a function over private data with
 out learning anything about the inputs other than the outcome of this comp
 utation. This offers a strong privacy guarantee: SFE enables, e.g., a medi
 cal researcher, a statistician, or a data analy...\n\n--------------------
 -\nBringing FPGAs to HPC Production Systems and Codes\n\nPlessl\n\nFPGA ar
 chitectures and development tools have made great strides towards a platfo
 rm for high-performant and energy-efficient computing, competing head to h
 ead with other processor and accelerator technologies. While we have seen 
 the first large-scale deployments of FPGAs in public and private clouds...
 \n\n---------------------\nFirst Steps in Porting the LFRic Weather and Cl
 imate Model to the FPGAs of the EuroExa Architecture\n\nAshworth, Riley, A
 ttwood, Mawer\n\nThe EuroExa project proposes a High-Performance Computing
  (HPC) architecture which is both scalable to exascale performance levels 
 and delivers world-leading power efficiency. This is achieved through the 
 use of low-power ARM processors accelerated by closely-coupled FPGA progra
 mmable components. In...\n\n---------------------\nIntegrating Network-Att
 ached FPGAs into the Cloud Using Partial Reconfiguration\n\nRinglein, Abel
 , Ditter\n\n---------------------\nThe MANGO Process for Designing and Pro
 gramming Multi-Accelerator Multi-FPGA Systems\n\nTornero, Flich, Martinez,
  Picornell, Scotti\n\nThis paper describes the approach followed in the Eu
 ropean FETHPC MANGO project to design and program systems made of multiple
  FPGAs interconnected. The MANGO approach relies on the instantiation and 
 management of multiple generic and custom-made accelerators which can be p
 rogrammed to communicate e...\n\n---------------------\nScalable FPGA Depl
 oyments for HPC and DC Applications\n\nHagleitner\n\nFPGAs have recently f
 ound their way and niche in large-scale data-center (DC) applications, eg,
  for endpoint encryption/compression, video transcoding, and genomics appl
 ications. We present two research projects that address two remaining road
 blocks on the way to scalable performance and energy-effi...\n\n----------
 -----------\nStream Computing of Lattice-Boltzmann Method on Intel Program
 mable Accelerator Card\n\nMiyajima, Ueno, Sano, Miyajima\n\nIntel Programm
 able Accelerator Card (Intel-PAC) and Open Programmable Acceleration Engin
 e (OPAE) aim at saving developers time and enabling code re-use across mul
 tiple FPGA platforms. We implemented a Lattice-Boltzmann Method (LBM) comp
 uting core, a computational fluid dynamics application, on Intel...\n\n---
 ------------------\nSimBSP: Enabling RTL Simulation for Intel FPGA OpenCL 
 Kernels\n\nHerbordt, Sanaullah\n\nRTL simulation is an integral step in FP
 GA development since it provides cycle accurate information regarding the 
 behavior and performance of custom architectures, without having to compil
 e the design to actual hardware. Despite its advantages, however, RTL simu
 lation is not currently supported by a...\n\n---------------------\nWorksh
 op Morning Break\n\n\n\n---------------------\nAccelerating Intelligence\n
 \nDavis\n\nMassive amounts of data are being consumed and processed to dri
 ve business. The exponential increase in data has not been matched by the 
 computational power of processors. This has led to the rise of accelerator
 s. However, big data algorithms for ETL, ML, AI, and DL are evolving rapid
 ly and/or have ...\n
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